Remarks on Improving of Operation Speed of The PLCs

Authors:	Milik Adam, Silesian University of Technology of Gliwice, Poland Hrynkiewicz Edward, Silesian University of Technology of Gliwice, Poland Chmiel Miroslaw, Silesian University of Technology of Gliwice, Poland
Topic:	4.1 Components and Instruments
Session:	Programmable Devices and Embedded Systems
Keywords:	Programmable Logic Controller; Central Processing Unit; Bit-Byte Structure of CPU; Control Program; Scan Time; Throughput Time; Reconfigurable Logic Controller; Programmable Logic Devices; Field Programmable Gate Arrays; Parallel Processing

Abstract

The paper presents two different approaches to optimising operation speed of Programmable Logic Controllers. First approach optimizes architecture of the CPU and the program execution. It shows the two processors bit-byte architecture which support of concurrent execution of bit and byte computation tasks. Second approach bases on hardware implemented control algorithm in reconfigurable platform based on FPGA. In second solution high performance is achieved by fully concurrent hardware execution of algorithm. Specific implementation tools enables typical PLC programming for hardware target platform. Copyright (C) 2005 IFAC